Semiconductor manufacturing economics necessitate the development of innovative device measurement techniques for quick assessment of products. Several novel electrical measurement techniques will be proposed for screening silicon device parameters. The studied parameters range from oxide reliability, and carrier lifetime in MOS capacitors to the power MOSFET reverse recovery.

It will be shown that positive charge trapping is a dominant process when thick oxides are stressed through the ramped voltage test (RVT). Exploiting the physics behind positive charge generation/trapping at high electric fields, a fast I-V measurement technique is proposed that can be used to effectively distinguish the ultra-thick oxides' intrinsic quality at low electric fields.

Next, two novel techniques will be presented for studying the carrier lifetime in MOS Capacitor devices. It will be shown that the deep-level transient spectroscopy (DLTS) can be applied to MOS test structures as a swift mean for screening the generation lifetime. Recombination lifetime will also be addressed by introducing the optically-excited MOS technique as a promising tool.

The last part of this work is devoted to the reverse recovery behavior of the body diode of power MOSFETs. The correct interpretation of the LDMOS reverse recovery is challenging and requires special attention. A simple approach will be presented to extract meaningful lifetime values from the reverse recovery of LDMOS body-diodes exploiting their gate voltage and the magnitude of the reverse bias.

Carrier lifetime is one of the few parameters which can give information about the low defect densities in today's semiconductors. In principle there is no lower limit to the defect density determined by lifetime measurements. No other technique can easily detect defect densities as low as 10-9 - 10-10 cm-3 in a simple, contactless room temperature measurement. However in practice, recombination lifetime τr measurements such as photoconductance decay (PCD) and surface photovoltage (SPV) that are widely used for characterization of bulk wafers face serious limitations when applied to thin epitaxial layers, where the layer thickness is smaller than the minority carrier diffusion length Ln. Other methods such as microwave photoconductance decay (µ-PCD), photoluminescence (PL), and frequency-dependent SPV, where the generated excess carriers are confined to the epitaxial layer width by using short excitation wavelengths, require complicated configuration and extensive surface passivation processes that make them time-consuming and not suitable for process screening purposes. Generation lifetime τg, typically measured with pulsed MOS capacitors (MOS-C) as test structures, has been shown to be an eminently suitable technique for characterization of thin epitaxial layers. It is for these reasons that the IC community, largely concerned with unipolar MOS devices, uses lifetime measurements as a "process cleanliness monitor." However when dealing with ultraclean epitaxial wafers, the classic MOS-C technique measures an effective generation lifetime τg eff which is dominated by the surface generation and hence cannot be used for screening impurity densities. I have developed a modified pulsed MOS technique for measuring generation lifetime in ultraclean thin p/p+ epitaxial layers which can be used to detect metallic impurities with densities as low as 10-10 cm-3. The widely used classic version has been shown to be unable to effectively detect such low impurity densities due to the domination of surface generation; whereas, the modified version can be used suitably as a metallic impurity density monitoring tool for such cases.