RISC-V Exceptions and Interrupts

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Description
RISC-V is an open-source processor architecture developed by students and faculty at the University of California at Berkeley. This document explores RISC-V exceptions and interrupts by clarifying how this computer architecture handles traps. The document defines the different exceptions and

RISC-V is an open-source processor architecture developed by students and faculty at the University of California at Berkeley. This document explores RISC-V exceptions and interrupts by clarifying how this computer architecture handles traps. The document defines the different exceptions and interrupts outlined in the RISC-V architecture and explains the different registers that are used by the trap handler. This document also briefly addresses concepts outside the purview of the RISC-V ISA like interrupt controllers which are important for understanding how these external events interact with the processor hardware.
Date Created
2020-12
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