The world has seen a revolution in cellular communication with the advent of 5G (fifth-generation), which enables gigabits per second data speed with low latency, massive capacity, and increased availability. These modern wireless systems improve spectrum efficiency by employing advanced modulation techniques, but result in large peak-to-average power ratios (PAPR) of the transmitted signals that degrades the efficiency of the radio-frequency power amplifiers (PAs) in the power back-off (PBO) region. Envelope tracking (ET), which is a dynamic supply control technology to realize high efficiency PAs, is a promising approach for designing transmitters for the future. Conventional voltage regulators, such as linear regulators and switching regulators, fail to simultaneously offer high speed, high efficiency, and improved linearity. Hybrid supply modulators (HSM) that combine a linear and switching regulator emerge as promising solutions to achieve an optimized tradeoff between different design parameters. Over the years, considerable development and research efforts in industry and academia have been spent on maximizing HSM performance, and a majority of the most recently developed modulators are implemented in CMOS technology and mainly targeted for handset applications. In this dissertation, the main requirements for modern HSM designs are categorized and analyzed in detail. Next, techniques to improve HSM performance are discussed. The available device technologies for HSM and PA implementations are also delineated, and implementation challenges of an integrated ET-PA system are summarized. Finally, a Current-Mode with Dynamic Hysteresis HSM is proposed, designed, and implemented. With the proposed technique, the HSM is able to track LTE signals up to 100 MHz bandwidth. Switching at a peak frequency of 40 MHz, the design is able to track a 1 Vpp sinusoidal signal with high fidelity, has an output voltage ripple around 54 mV, and achieves a peak static and dynamic efficiency of 92.2% and 82.29%, respectively, at the maximum output. The HSM is capable of delivering a maximum output power of 425 mW and occupies a small die area of 1.6mm2. Overall, the proposed HSM promises competitive performance compared to state-of-the-art works.

This work covers the design and implementation of a Parallel Doherty RF Power Amplifier in a GaN HEMT process for medium power macro-cell (16W) base station applications. This work improves the key parameters of a Doherty Power Amplifier including the peak and back-off efficiency, operational instantaneous bandwidth and output power by proposing a Parallel Doherty amplifier architecture.

As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals.

The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals.