This research aims to investigate the material properties of various silver-doped germanium-chalcogenide thin films that novel lateral Programmable Metallization Cell (PMC) devices are based on. These devices are governed by a solid-state electrochemical reaction that is controlled electrically occurring at the micro and nanoscale.By using various electrical and optical characterization techniques, useful material characteristics such as the activation energy of electrodeposit growth rate and bandgap energy can be extracted. These parameters allow for better tuning of these materials for more specific PMC device applications, such as a timer that can be placed into integrated circuits for metering and anticounterfeiting purposes. The compositions of focus are silver-doped germanium-selenide and germanium-sulfide variations; overall, the bandgap energy of these materials decreases as silver content is increased, the activation energy tends to be smaller in sulfide-based devices, and chalcogenides highly doped with silver exhibit nanocluster migration growth modes due to the agglomeration of silver clusters in the film.

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.