Characterization and Testing of the Weighted-Overlap-and-Add High-Speed Polyphase Filterbank

The Discrete Fourier Transform (DFT) is a mathematical operation utilized in various signal processing applications including Astronomy and digital communications (satellite, cellphone, radar, etc.) to separate signals at different frequencies. Performing DFT on a signal by itself suffers from inter-channel leakage. For an ultrasensitive application like radio astronomy, it is important to minimize frequency sidelobes. To achieve this, the Polyphase Filterbank (PFB) technique is used which modifies the bin-response of the DFT to a rectangular function and suppresses out-of-band crosstalk. This helps achieve the Signal-to-Noise Ratio (SNR) required for astronomy measurements. In practice, 2N DFT can be efficiently implemented on Digital Signal Processing (DSP) hardware by the popular Fast Fourier Transform (FFT) algorithm. Hence, 2N tap-filters are commonly used in the Filterbank stage before the FFT. At present, Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) from different vendors (e.g. Xilinx, Altera, Microsemi, etc.) are available which offer high performance. Xilinx Radio-Frequency System-on-Chip (RFSoC) is the latest kind of such a platform offering Radio-frequency (RF) signal capture / generate capability on the same chip. This thesis describes the characterization of the Analog-to-Digital Converter (ADC) available on the Xilinx ZCU111 RFSoC platform, detailed design steps of a Critically-Sampled PFB, and the testing and debugging of a Weighted OverLap and Add (WOLA) PFB to examine the feasibility of implementation on custom ASICs for future space missions. The design and testing of an analog Printed Circuit Board (PCB) circuit for biasing cryogenic detectors and readout components are also presented here.