GaAs Thermophotovoltaic Cells with Patterned Dielectric Back Contact

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Description
GaAs thermophotovoltaic (TPV) devices with a patterned dielectric back contact (PDBC) architecture, featuring a dielectric spacer between the semiconductor and back metal contact over most of the back surface for high reflectance, and metal point contacts over a smaller area

GaAs thermophotovoltaic (TPV) devices with a patterned dielectric back contact (PDBC) architecture, featuring a dielectric spacer between the semiconductor and back metal contact over most of the back surface for high reflectance, and metal point contacts over a smaller area for electrical conduction were demonstrated. In the TPV application, high sub-bandgap reflectance is needed to reflect unused sub-bandgap photons to the thermal emitter to minimize energy losses in this portion of the thermal spectrum. Different PDBC fabrication processes with SU-8 and SiO2 dielectric spacer layers to maximize sub-bandgap reflectance while minimizing series resistance to increase TPV conversion efficiency was explored. GaAs SU-8 PDBC TPV devices with 2200°C blackbody-weighted sub-bandgap reflectance of 94.9% and 96.5% with and without a front metal grid, respectively were demonstrated. This was 0.7% and 2.3% (absolute) higher than the mean sub-bandgap reflectance of 94.2% for GaAs baseline TPV devices with 100% Au back contact with a front metal grid. Lower sub-bandgap reflectance in TPV devices with front grids indicated the front grid induced light scattering led to additional parasitic absorption in the TPV device. For higher contact coverage fractions, the PDBC reflectance cannot, in general, be treated by linear interpolation of the mirror and point-contact areas using simple 1D transfer matrix method modeling and should be treated instead as a diffraction grating by solving Maxwell's equations in 3D. GaAs PDBC TPV device with series resistance less than 10 mΩ·cm2 was demonstrated. Finally, GaAs PDBC TPV device with 22.8% TPV efficiency measured in a thermophotovoltaic test platform with the thermal emitter at 2100℃ was demonstrated