Passive Loop Filter Zoom Analog to Digital Converters

This dissertation proposes and presents two different passive sigma-delta

modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step

by step process designing the zoom-ADC along with a synthesis tool that can target various

design specifications are presented. The design flow does not rely on extensive knowledge

of an experienced ADC designer. Two example set of BIST ADCs have been synthesized

with different performance requirements in 65nm CMOS process. The first ADC achieves

90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW

power. Another example achieves 78.2dB SNR in 31.25µs measurement time and

consumes 63µW power. The second ADC architecture is a multi-mode, dynamically

zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating

flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the

fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-

independent, dynamic zooming technique, employing an interpolating zooming front-end.

The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it

suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,

bias current, and component parameters, optimal power consumption can be achieved for

every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an

SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW

power consumption from a 1.2 V supply.