Readout Integrated Circuits(ROICs) are important components of infrared(IR) imag

ing systems. Performance of ROICs affect the quality of images obtained from IR

imaging systems. Contemporary infrared imaging applications demand ROICs that

can support large dynamic range, high frame rate, high output data rate, at low

cost, size and power. Some of these applications are military surveillance, remote

sensing in space and earth science missions and medical diagnosis. This work focuses

on developing a ROIC unit cell prototype for National Aeronautics and Space Ad

ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These

space applications also demand high sensitivity, longer integration times(large well

capacity), wide operating temperature range, wide input current range and immunity

to radiation events such as Single Event Latchup(SEL).

This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,

to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared

Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range

of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.

The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and

supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per

second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.

The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling

integration times as long as 10ms, to achieve better dynamic range. The DROIC unit

cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.

The proposed DROIC uses layout techniques that make it immune to radiation up to

300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a

wide input current range from 10pA to 1uA and supports detectors operating from

Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.

Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.

The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.

The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.

A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of

over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-

put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.

This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:

1) A transformer-based power combiner architecture for out-phasing transmitters

2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)

3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters

This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.

The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.

Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.

Power management circuits are employed in most electronic integrated systems, including applications for automotive, IoT, and smart wearables. Oftentimes, these power management circuits become a single point of system failure, and since they are present in most modern electronic devices, they become a target for hardware security attacks. Digital circuits are typically more prone to security attacks compared to analog circuits, but malfunctions in digital circuitry can affect the analog performance/parameters of power management circuits. This research studies the effect that these hacks will have on the analog performance of power circuits, specifically linear and switching power regulators/converters. Apart from security attacks, these circuits suffer from performance degradations due to temperature, aging, and load stress. Power management circuits usually consist of regulators or converters that regulate the load’s voltage supply by employing a feedback loop, and the stability of the feedback loop is a critical parameter in the system design. Oftentimes, the passive components employed in these circuits shift in value over varying conditions and may cause instability within the power converter. Therefore, variations in the passive components, as well as malicious hardware security attacks, can degrade regulator performance and affect the system’s stability. The traditional ways of detecting phase margin, which indicates system stability, employ techniques that require the converter to be in open loop, and hence can’t be used while the system is deployed in-the-field under normal operation. Aging of components and security attacks may occur after the power management systems have completed post-production test and have been deployed, and they may not cause catastrophic failure of the system, hence making them difficult to detect. These two issues of component variations and security attacks can be detected during normal operation over the product lifetime, if the frequency response of the power converter can be monitored in-situ and in-field. This work presents a method to monitor the phase margin (stability) of a power converter without affecting its normal mode of operation by injecting a white noise/ pseudo random binary sequence (PRBS). Furthermore, this work investigates the analog performance parameters, including phase margin, that are affected by various digital hacks on the control circuitry associated with power converters. A case study of potential hardware attacks is completed for a linear low-dropout regulator (LDO).

State-of-the-art automotive radars use multi-chip Frequency Modulated Continuous Wave (FMCW) radars to sense the environment around the car. FMCW radars are prone to interference as they operate over a narrow baseband bandwidth and use similar radio frequency (RF) chirps among them. Phase Modulated Continuous Wave radars (PMCW) are robust and insensitive to interference as they transmit signals over a wider bandwidth using spread spectrum technique. As more and more cars are equipped with FMCW radars illuminate the same environment, interference would soon become a serious issue. PMCW radars can be an effective solution to interference in the noisy FMCW radar environment. PMCW radars can be implemented in silicon as System-on-a-chip (SoC), suitable for Multiple-Input-Multiple-Output (MIMO) implementation and is highly programmable. PMCW radars do not require highly linear high frequency chirping oscillators thus reducing the size of the final solution.

This thesis aims to present a behavior model for this promising Digitally modulated radar (DMR) transceiver in Simulink/Matlab. The goal of this work is to create a model for the electronic system level framework that simulates the entire system with non-idealities. This model includes a Top Down Design methodology to understand the requirements of the individual modules’ performance and thus derive the specifications for implementing the real chip. Back annotation of the actual electrical modules’ performance to the model closes the design process loop. Using Simulink’s toolboxes, a passband and equivalent baseband model of the system is built for the transceiver with non-idealities of the components built in along with signal processing routines in Matlab. This model provides a platform for system evaluation and simulation for various system scenarios and use-cases of sensing using the environment around a moving car.

Space exploration is a large field that requires high performing circuitry due to the harsh environment. Within a space environment one of the biggest factors leading to circuit failure is radiation. Circuits must be robust enough to continue operation after being exposed to the high doses of radiation. Bandgap reference (BGR) circuits are designed to be voltage references that stay stable across a wide range of supply voltages and temperatures. A bandgap reference is a piece of a large circuit that supplies critical elements of the large circuit with a constant voltage. When used in a space environment with large amounts of radiation a BGR needs to maintain its output voltage to enable the rest of the circuit to operate under proper conditions. Since a BGR is not a standalone circuit it is difficult and expensive to test if a BGR is maintaining its reference voltage.

This thesis describes a methodology of isolating and simulating bandgap references. Both NPN and PNP bandgap references are simulated over a variety of radiation doses and dose rates. This methodology will allow the degradation due to radiation of a BGR to be modeled easily and affordably. It can be observed that many circuits experience enhanced low dose rate sensitivity (ELDRS) which can lead to failure at low total ionizing doses (TID) of radiation. A compact model library demonstrating degradation of transistors at both high and low dose rates (HDR and LDR) will be used to show bandgap references reliability. Specifically, two bandgap references being utilized in commercial off the shelf low dropout regulators (LDO) will be evaluated. The LDOs are reverse engineered in a simulation program with integrated circuit emphasis (SPICE). Within the two LDOs the bandgaps will be the points of interest. Of the LDOs one has a positive regulated voltage and one has a negative regulated voltage. This requires an NPN and a PNP based BGR respectively. This simulation methodology will draw conclusions about the above bandgap references, and how they operate under radiation at different doses and dose rates.

There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.

This thesis outlines the hand-held memory characterization testing system that is to be created into a PCB (printed circuit board). The circuit is designed to apply voltages diagonally through a RRAM cell (32x32 memory array). The purpose of this sweep across the RRAM is to measure and calculate the high and low resistance state value over a specified amount of testing cycles. With each cell having a unique output of high and low resistance states a unique characterization of each RRAM cell is able to be developed. Once the memory is characterized, the specific RRAM cell that was tested is then able to be used in a varying amount of applications for different things based on its uniqueness. Due to an inability to procure a packaged RRAM cell, a Mock-RRAM was instead designed in order to emulate the same behavior found in a RRAM cell.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.

There is an increasing demand for fully integrated point-of-load (POL) isolated DC-DC converters that can provide an isolation barrier between the primary and the secondary side, while delivering a low ripple, low noise regulated voltage at their isolated sides to a high dynamic range, sensitive mixed signal devices, such as sensors, current-shunt-monitors and ADCs. For these applications, smaller system size and integration level is important because the whole system may need to fit to limited space. Traditional methods for providing isolated power are discrete solutions using bulky transformers. Miniaturization of isolated POL regulators is becoming highly desirable for low power applications.

A fully integrated, low noise isolated point-of-load DC-DC converter for supply regulation of high dynamic range analog and mixed signal sensor signal-chains is presented. The isolated DC-DC converter utilizes an integrated planar air-core micro-transformer as a coupled resonator and isolation barrier and enables direct connection of low-voltage mixed signal circuits to higher supply rails. The air core transformer is driven at its primary resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The isolated converter’s output ripple is reduced by utilizing spread spectrum clocking in the driver. An isolated PMOS LDO in the secondary side is used to suppress switching noise and ripple by 21dB. Conducted and radiated EMI distribution on the IC is measured by a set of integrated ring oscillator based noise sensors with -68dBm noise sensitivity. The proposed isolated converter achieves highest level of integration with respect to earlier reported integrated isolated converters, while providing 50V on-chip junction isolation without the need for extra silicon post-processing steps.