The scaling of transistors has numerous advantages such as increased memory density, less power consumption and better performance; but on the other hand, they also give rise to many reliability issues. One of the major reliability issue is the hot carrier injection and the effect it has on device degradation over time which causes serious circuit malfunctions.

Hot carrier injection has been studied from early 1980's and a lot of research has been done on the various hot carrier injection mechanisms and how the devices get damaged due to this effect. However, most of the existing hot carrier degradation models do not consider the physics involved in the degradation process and they just calculate the change in threshold voltage for different stress voltages and time. Based on this, an analytical expression is formulated that predicts the device lifetime.

This thesis starts by discussing various hot carrier injection mechanisms and the effects it has on the device. Studies have shown charges getting trapped in gate oxide and interface trap generation are two mechanisms for device degradation. How various device parameters get affected due to these traps is discussed here. The physics based models such as lucky hot electron model and substrate current model are presented and gives an idea how the gate current and substrate current can be related to hot carrier injection and density of traps created.

Devices are stressed under various voltages and from the experimental data obtained, the density of trapped charges and interface traps are calculated using mid-gap technique. In this thesis, a simple analytical model based on substrate current is used to calculate the density of trapped charges in oxide and interface traps generated and it is a function of stress voltage and stress time. The model is verified against the data and the TCAD simulations. Finally, the analytical model is incorporated in a Verilog-A model and based on the surface potential method, the threshold voltage shift due to hot carrier stress is calculated.

Counterfeiting of goods is a widespread epidemic that is affecting the world economy. The conventional labeling techniques are proving inadequate to thwart determined counterfeiters equipped with sophisticated technologies. There is a growing need of a secure labeling that is easy to manufacture and analyze but extremely difficult to copy. Programmable metallization cell technology operates on a principle of controllable reduction of a metal ions to an electrodeposit in a solid electrolyte by application of bias. The nature of metallic electrodeposit is unique for each instance of growth, moreover it has a treelike, bifurcating fractal structure with high information capacity. These qualities of the electrodeposit can be exploited to use it as a physical unclonable function. The secure labels made from the electrodeposits grown in radial structure can provide enhanced authentication and protection from counterfeiting and tampering.

So far only microscale radial structures and electrodeposits have been fabricated which limits their use to labeling only high value items due to high cost associated with their fabrication and analysis. Therefore, there is a need for a simple recipe for fabrication of macroscale structure that does not need sophisticated lithography tools and cleanroom environment. Moreover, the growth kinetics and material characteristics of such macroscale electrodeposits need to be investigated. In this thesis, a recipe for fabrication of centimeter scale radial structure for growing Ag electrodeposits using simple fabrication techniques was proposed. Fractal analysis of an electrodeposit suggested information capacity of 1.27 x 1019. The kinetics of growth were investigated by electrical characterization of the full cell and only solid electrolyte at different temperatures. It was found that mass transport of ions is the rate limiting process in the growth. Materials and optical characterization techniques revealed that the subtle relief like structure and consequently distinct optical response of the electrodeposit provides an added layer of security. Thus, the enormous information capacity, ease of fabrication and simplicity of analysis make macroscale fractal electrodeposits grown in radial programmable metallization cells excellent candidates for application as physical unclonable functions.

The instrumentational measurement of seismic motion is important for a wide range of research fields and applications, such as seismology, geology, physics, civil engineering and harsh environment exploration. This report presents series approaches to develop Micro-Electro-Mechanical System (MEMS) enhanced inertial motion sensors including accelerometers, seismometers and inclinometers based on Molecular Electronic Transducers (MET) techniques.

Seismometers based on MET technology are attractive for planetary applications due to their high sensitivity, low noise floor, small size, absence of fragile mechanical moving parts and independence on the direction of sensitivity axis. By using MEMS techniques, a micro MET seismometer is developed with inter-electrode spacing close to 5 μm. The employment of MEMS improves the sensitivity of fabricated device to above 2500 V/(m/s2) under operating bias of 300 mV and input velocity of 8.4μm/s from 0.08Hz to 80Hz. The lowered hydrodynamic resistance by increasing the number of channels improves the self-noise to -135 dB equivalent to 18nG/√Hz (G=9.8m/s2) around 1.2 Hz.

Inspired by the advantages of combining MET and MEMS technologies on the development of seismometer, a feasibility study of development of a low frequency accelerometer utilizing MET technology with post-CMOS-compatible fabrication processes is performed. In the fabricated accelerometer, the complicated fabrication of mass-spring system in solid-state MEMS accelerometer is replaced with a much simpler post-CMOS-compatible process containing only deposition of a four-electrode MET structure on a planar substrate, and a liquid inertia mass of an electrolyte droplet. With a specific design of 3D printing based package and replace water based iodide solution by room temperature ionic liquid based electrolyte, the sensitivity relative to the ground motion can reach 103.69V/g, with the resolution of 5.25μG/√Hz at 1Hz.

By combining MET techniques and Zn-Cu electrochemical cell (Galvanic cell), this letter demonstrates a passive motion sensor powered by self-electrochemistry energy, named “Battery Accelerometer”. The experimental results indicated the peak sensitivity of battery accelerometer at its resonant frequency 18Hz is 10.4V/G with the resolution of 1.71μG without power consumption.

Layers of intrinsic hydrogenated amorphous silicon and amorphous silicon carbide

were prepared on a polished, intrinsic crystalline silicon substrate via plasma-enhanced chemical vapor deposition to simulate heterojunction device relevant stacks of various materials. The minority carrier lifetime, optical band gap and FTIR spectra were observed at incremental stages of thermal annealing. By observing the changes in the lifetimes the sample structure responsible for the most thermally robust surface passivation could be determined. These results were correlated to the optical band gap and the position and relative area of peaks in the FTIR spectra related to to silicon-hydrogen bonds in the layers. It was found that due to an increased presence of hydrogen bonded to silicon at voids within the passivating layer, hydrogenated amorphous silicon carbide at the interface of the substrate coupled with a hydrogenated amorphous silicon top layer provides better passivation after high temperature annealing than other device structures.

In the nano-regime many materials exhibit properties that are quite different from their bulk counterparts. These nano-properties have been shown to be useful in a wide range of applications with nanomaterials being used for catalysts, in energy production, as protective coatings, and in medical treatment. While there is no shortage of exciting and novel applications, the world of nanomaterials suffers from a lack of large scale manufacturing techniques. The current methods and equipment used for manufacturing nanomaterials are generally slow, expensive, potentially dangerous, and material specific. The research and widespread use of nanomaterials has undoubtedly been hindered by this lack of appropriate tooling. This work details the effort to create a novel nanomaterial synthesis and deposition platform capable of operating at industrial level rates and reliability.

The tool, referred to as Deppy, deposits material via hypersonic impaction, a two chamber process that takes advantage of compressible fluids operating in the choked flow regime to accelerate particles to up several thousand meters per second before they impact and stick to the substrate. This allows for the energetic separation of the synthesis and deposition processes while still behaving as a continuous flow reactor giving Deppy the unique ability to independently control the particle properties and the deposited film properties. While the ultimate goal is to design a tool capable of producing a broad range of nanomaterial films, this work will showcase Deppy's ability to produce silicon nano-particle films as a proof of concept.

By adjusting parameters in the upstream chamber the particle composition was varied from completely amorphous to highly crystalline as confirmed by Raman spectroscopy. By adjusting parameters in the downstream chamber significant variation of the film's density was achieved. Further it was shown that the system is capable of making these adjustments in each chamber without affecting the operation of the other.

Alternative computation based on neural systems on a nanoscale device are of increasing interest because of the massive parallelism and scalability they provide. Neural based computation systems also offer defect finding and self healing capabilities. Traditional Von Neumann based architectures (which separate the memory and computation units) inherently suffer from the Von Neumann bottleneck whereby the processor is limited by the number of instructions it fetches. The clock driven based Von Neumann computer survived because of technology scaling. However as transistor scaling is slowly coming to an end with channel lengths becoming a few nanometers in length, processor speeds are beginning to saturate. This lead to the development of multi-core systems which process data in parallel, with each core being based on the Von Neumann architecture.

The human brain has always been a mystery to scientists. Modern day super computers are outperformed by the human brain in certain computations. The brain occupies far less space and consumes a fraction of the power a super computer does with certain processes such as pattern recognition. Neuromorphic computing aims to mimic biological neural systems on silicon to exploit the massive parallelism that neural systems offer. Neuromorphic systems are event driven systems rather than being clock driven. One of the issues faced by neuromorphic computing was the area occupied by these circuits. With recent developments in the field of nanotechnology, memristive devices on a nanoscale have been developed and show a promising solution. Memristor based synapses can be up to three times smaller than Complementary Metal Oxide Semiconductor (CMOS) based synapses.

In this thesis, the Programmable Metallization Cell (a memristive device) is used to prove a learning algorithm known as Spike Time Dependant Plasticity (STDP). This learning algorithm is an extension to Hebb’s learning rule in which the synapses weight can be altered by the relative timing of spikes across it. The synaptic weight with the memristor will be its conductance, and CMOS oscillator based circuits will be used to produce spikes that can modulate the memristor conductance by firing with different phases differences.

Non-volatile memory (NVM) has become a staple in the everyday life of consumers. NVM manifests inside cell phones, laptops, and most recently, wearable tech such as smart watches. NAND Flash has been an excellent solution to conditions requiring fast, compact NVM. Current technology nodes are nearing the physical limits of scaling, preventing flash from improving. To combat the limitations of flash and to appease consumer demand for progressively faster and denser NVM, new technologies are needed. One possible candidate for the replacement of NAND Flash is programmable metallization cells (PMC). PMC are a type of resistive memory, meaning that they do not rely on charge storage to maintain a logic state. Depending on their application, it is possible that devices containing NVM will be exposed to harsh radiation environments. As part of the process for developing a novel memory technology, it is important to characterize the effects irradiation has on the functionality of the devices.

This thesis characterizes the effects that ionizing γ-ray irradiation has on the retention of the programmed resistive state of a PMC. The PMC devices tested used Ge30Se70 doped with Ag as the solid electrolyte layer and were fabricated by the thesis author in a Class 100 clean room. Individual device tiles were wire bonded into ceramic packages and tested in a biased and floating contact scenario.

The first scenario presented shows that PMC devices are capable of retaining their programmed state up to the maximum exposed total ionizing dose (TID) of 3.1 Mrad(Si). In this first scenario, the contacts of the PMC devices were left floating during exposure. The second scenario tested shows that the PMC devices are capable of retaining their state until the maximum TID of 10.1 Mrad(Si) was reached. The contacts in the second scenario were biased, with a 50 mV read voltage applied to the anode contact. Analysis of the results show that Ge30Se70 PMC are ionizing radiation tolerant and can retain a programmed state to a higher TID than NAND Flash memory.

A new loop configuration capable of reducing power radiation magnitudes lower than conventional loops has been developed. This configuration is demonstrated for the case of two coaxial loops of 0.1 meter radius coupled via the magnetic reactive field. Utilizing electromagnetism theory, techniques from antenna design and a new near field design initiative, the ability to design a magnetic field has been investigated by using a full wave simulation tool. The method for realization is initiated from first order physics model, ADS and onto a full wave situation tool for the case of a non-radiating helical loop. The exploration into the design of a magnetic near field while mitigating radiation power is demonstrated using an real number of twists to form a helical wire loop while biasing the integer twisted loop in a non-conventional moebius termination. The helix loop setup as a moebius loop convention can also be expressed as a shorted antenna scheme. The 0.1 meter radius helix antenna is biased with a 1MHz frequency that categorized the antenna loop as electrically small. It is then demonstrated that helical configuration reduces the electric field and mitigates power radiation into the far field. In order to compare the radiated power reduction performance of the helical loop a shielded loop is used as a baseline for comparison. The shielded loop system of the same geometric size and frequency is shown to have power radiation expressed as -46.1 dBm. The power radiated mitigation method of the helix loop reduces the power radiated from the two loop system down to -98.72 dBm.

Several state of the art, monitoring and control systems, such as DC motor

controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.